The present invention is generally directed to an improved system for converting a floating point n-bit signed magnitude binary number to a fixed point two's complement m-bit binary number wherein m is greater than n. The system of the present invention has particular utility in a multiplier system which multiplies two signed magnitude operands together.
Systems for multiplying two signed magnitude operands together to provide an n-bit signed magnitude binary number are well known in the art. Such systems multiply the operand magnitudes and add the operand exponents. Often, it is desired to format the multiplication product in fixed point two's complement m-bit form wherein m is greater than n to account for the exponent.
In the prior art, the conversion of a signed magnitude binary number to a two's complement binary number for such an application required two steps. First, the signed magnitude product is scaled in a left-right shifter wherein the n-bit product is shifted to the left or the right and by a number of bits depending upon the exponent of the multiplication product to provide a corresponding fixed point signed magnitude m-bit binary number. Then, the m-bit signed magnitude binary number is converted to a corresponding m-bit two's complement binary number.
The foregoing conversion technique requires considerable hardware and time to achieve the required conversion. The conversion to two's complement generally requires a chain of half adder cells with a half adder cell being provided for each signed magnitude bit. As a result, if the signed magnitude m-bit binary number contains fifteen bits, for example, fifteen half adder cells are required to effect the conversion. Furthermore, in such a case, the delay time in the two's complement converter is represented by the chain of fifteen half adder cells.
The present invention provides an alternative approach for converting a floating point n-bit signed magnitude binary number to a fixed point m-bit two's complement binary number which requires less time and hardware to achieve the conversion. For example, if the magnitude of the signed magnitude binary number contains eight bits and the final fixed point two's complement binary number contains fifteen bits, seven less half adder cells are required as compared to the prior art method. This not only represents less hardware, but also represents less conversion delay time because of the reduced number of required half adder cells.